1. Field of the Invention
This invention relates to a semiconductor memory, in particular, a static random access memory (hereinafter referred to as “SRAM”) formed of FinFETs.
2. Description of the Related Art
Generally, when a memory cell for an SRAM (hereinafter referred to as “SRAM cell”) is designed, a good data-holding property is secured by setting the device resistance of a transfer gate transistor to a value higher than that of the device resistance of a drive transistor. Specifically, this is achieved by providing a driver transistor having a shorter channel length (L) and a wider channel width (W) than those of the transfer gate transistor.
Recently, as a transistor of a new structure, Fin typed Double-Gate MIS field effect transistor (hereinafter referred to as “FinFET”) having a three-dimensional structure receive attention. The FinFET has the following structure.
A single-crystal silicon layer of an SOI (silicon on insulator) substrate is processed into rectangular pieces to form projecting regions (hereinafter referred to as “fin layer”) being semiconductor regions. A gate electrode is crossed over the fin layer, and thereby the fin layer is used as a channel (for example, please refer to Jpn. Pat. Appln. KOKAI Pub. No. 2-263473).
SRAMs formed of the FinFETs have been proposed (for example, please refer to E. J. Nowak et al., “A Functional FinFET-DGCMOS SRAM Cell”, IEDM 2002. Technical Digest, pp 411–414). FIG. 1 is a layout diagram illustrating an SRAM cell formed of FinFETs. FIG. 2 is a layout diagram illustrating a cell array of an SRAM, in which the SRAM cells are arranged. As shown in FIG. 1, an SRAM cell 100 is a 6-transistor SRAM cell, which is formed of six transistors. Specifically, the SRAM cell 100 comprises two drive transistors 101 and 102, two transfer gate transistors 103 and 104, and two load transistors 105 and 106.
However, since the channel width (W) of a FinFET depends on the height of the fin layers, it is difficult from the viewpoint of the process to allow the transistors to have different channel widths (W). Therefore, there is a problem that it is difficult to obtain a good data-holding property with an SRAM formed of FinFETs.